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DISCRETE SEMICONDUCTORS
DATA SHEET
PSMN015-100B; PSMN015-100P N-channel TrenchMOS(TM) transistor
Product specification August 1999
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
FEATURES
* 'Trench' technology * Very low on-state resistance * Fast switching * Low thermal resistance
g
PSMN015-100B; PSMN015-100P
QUICK REFERENCE DATA
SYMBOL
d
VDSS = 100 V ID = 75 A RDS(ON) 15 m
s
GENERAL DESCRIPTION
SiliconMAX products use the latest Philips Trench technology to achieve the lowest possible on-state resistance in each package at each voltage rating. Applications:* d.c. to d.c. converters * switched mode power supplies The PSMN015-100P is supplied in the SOT78 (TO220AB) conventional leaded package. The PSMN015-100B is supplied in the SOT404 surface mounting package.
PINNING
PIN 1 2 3 tab gate drain1 source drain DESCRIPTION
SOT78 (TO220AB)
tab
SOT404 (D2PAK)
tab
2
1 23
1
3
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage Continuous drain current Pulsed drain current Total power dissipation Operating junction and storage temperature CONDITIONS Tj = 25 C to 175C Tj = 25 C to 175C; RGS = 20 k Tmb = 25 C Tmb = 100 C Tmb = 25 C Tmb = 25 C MIN. - 55 MAX. 100 100 20 752 53 240 230 175 UNIT V V V A A A W C
1 It is not possible to make connection to pin:2 of the SOT404 package 2 Maximum continuous current limited by package
August 1999
2
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
AVALANCHE ENERGY LIMITING VALUES
PSMN015-100B; PSMN015-100P
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 74 A; tp = 100 s; Tj prior to avalanche = 25C; VDD 50 V; RGS = 50 ; VGS = 10 V; refer to fig:15 MIN. MAX. 481 UNIT mJ
IAS
-
75
A
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-mb Rth j-a Thermal resistance junction to mounting base Thermal resistance junction to ambient CONDITIONS TYP. SOT78 package, in free air SOT404 package, pcb mounted, minimum footprint 60 50 MAX. 0.65 UNIT K/W K/W K/W
ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 0.25 mA; Tj = -55C VDS = VGS; ID = 1 mA Tj = 175C Tj = -55C Drain-source on-state VGS = 10 V; ID = 25 A resistance Gate source leakage current VGS = 10 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance Tj = 175C Tj = 175C MIN. 100 89 2.0 1.0 TYP. MAX. UNIT 3.0 12 2 0.05 109 20 50 30 80 150 95 3.5 4.5 7.5 4720 650 380 4.0 6 15 41 100 10 500 V V V V V m m nA A A nC nC nC ns ns ns ns nH nH nH pF pF pF
ID = 75 A; VDD = 80 V; VGS = 10 V
VDD = 50 V; RD = 1.8 ; VGS = 10 V; RG = 5.6 Resistive load Measured from tab to centre of die Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 25 V; f = 1 MHz
August 1999
3
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN015-100B; PSMN015-100P
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr CONDITIONS MIN. TYP. MAX. UNIT 0.8 90 0.3 75 240 1.2 A A V ns C Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage IF = 25 A; VGS = 0 V Reverse recovery time Reverse recovery charge IF = 20 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 30 V
August 1999
4
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN015-100B; PSMN015-100P
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 150 Mounting Base temperature, Tmb (C) 175
1
Transient thermal impedance, Zth j-mb (K/W) D = 0.5 0.2
0.1
0.1 0.05 0.02
P D
0.01 single pulse
tp
D = tp/T
T
0.001 1E-06
1E-05
1E-04
1E-03
1E-02
1E-01
1E+00
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tmb)
Fig.4. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 15V 10 V 5V Tj = 25 C
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 125 Mounting Base temperature, Tmb (C) 150 175
50 45 40 35 30 25 20 15 10 5 0 0
4.6 V
4.4 V 4.2 V 4V 3.8 V 3.6 V 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tmb)
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS); parameter VGS
1000
Drain-Source On Resistance, RDS(on) (Ohms) 0.05 0.045 tp = 10 us 100 us 0.04 0.035 0.03 0.025 4V 4.2 V 4.4 V 4.6 V Tj = 25 C
RDS(on) = VDS/ ID
100
10
D.C.
1 ms 10 ms 100 ms
0.02 0.015 0.01 0.005
5V 10 V VGS = 15V
1 1 10 100 Drain-Source Voltage, VDS (V) 1000
0 0 5 10 15 20 25 30 Drain Current, ID (A) 35 40 45 50
Fig.3. Safe operating area. Tmb = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(VGS)
August 1999
5
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN015-100B; PSMN015-100P
Drain current, ID (A) 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Gate-source voltage, VGS (V) 175 C Tj = 25 C VDS > ID X RDS(ON)
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
Threshold Voltage, VGS(TO) (V) maximum typical
minimum
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS); parameter Tj
Transconductance, gfs (S) VDS > ID X RDS(ON) 70 Tj = 25 C 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Drain current, ID (A) 175 C
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
80
1.0E-01
Drain current, ID (A)
1.0E-02 minimum typical 1.0E-04 maximum 1.0E-05
1.0E-03
1.0E-06 0 0.5 1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V) 4 4.5 5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Fig.11. Sub-threshold drain current. ID = f(VGS); Tj = 25 C
Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C) Capacitances, Ciss, Coss, Crss (pF) 10000 Ciss
1000 Coss Crss
100 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
6
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
PSMN015-100B; PSMN015-100P
Maximum Avalanche Current, IAS (A) Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 75A Tj = 25 C VDD = 20 V 10 VDD = 80 V 25 C 100
Tj prior to avalanche = 150 C
10
20
30
40 50 60 70 80 Gate charge, QG (nC)
90
100 110 120
1 0.001
0.01
0.1 Avalanche time, tAV (ms)
1
10
Fig.13. Typical turn-on gate-charge characteristics VGS = f(QG)
Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tAV); unclamped inductive load
Source-Drain Diode Current, IF (A) 100 90 80 70 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Source-Drain Voltage, VSDS (V) 175 C Tj = 25 C VGS = 0 V
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
7
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
MECHANICAL DATA
PSMN015-100B; PSMN015-100P
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220
SOT78
E P
A A1 q
D1
D
L2(1)
L1 Q
L
b1
1
2
3
b c
e
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.5 4.1 A1 1.39 1.27 b 0.9 0.7 b1 1.3 1.0 c 0.7 0.4 D 15.8 15.2 D1 6.4 5.9 E 10.3 9.7 e 2.54 L 15.0 13.5 L1 3.30 2.79 L2 max. 3.0
(1)
P 3.8 3.6
q 3.0 2.7
Q 2.6 2.2
Note 1. Terminals in this zone are not tinned. OUTLINE VERSION SOT78 REFERENCES IEC JEDEC TO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-06-11
Fig.16. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to mounting instructions for SOT78 (TO220AB) package. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
8
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
MECHANICAL DATA
PSMN015-100B; PSMN015-100P
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads (one lead cropped)
SOT404
A E A1 mounting base
D1
D
HD
2
Lp
1
3
b c Q
e
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 4.50 4.10 A1 1.40 1.27 b 0.85 0.60 c 0.64 0.46 D max. 11 D1 1.60 1.20 E 10.30 9.70 e 2.54 Lp 2.90 2.10 HD 15.40 14.80 Q 2.60 2.20
OUTLINE VERSION SOT404
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 98-12-14 99-06-25
Fig.17. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
9
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
MOUNTING INSTRUCTIONS
Dimensions in mm
PSMN015-100B; PSMN015-100P
11.5
9.0
17.5 2.0
3.8
5.08
Fig.18. SOT404 : soldering pattern for surface mounting.
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
10
Rev 1.100
Philips Semiconductors
Product specification
N-channel TrenchMOS(TM) transistor
NOTES
PSMN015-100B; PSMN015-100P
August 1999
11
Rev 1.100
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000
Internet: http://www.semiconductors.philips.com
SCA 69
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
603502/300/03/pp12
Date of release: August
1999
Document order number:
9397 750 06974

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